Language Breakdown
Lines of code distribution across 28 owned repositories
18.1M
Total LOC
Verilog
17,458,285 lines
96.7%
N/A
SystemVerilog
273,719 lines
1.5%
N/A
C
139,805 lines
0.8%
N/A
Makefile
56,894 lines
0.3%
N/A
C++
40,776 lines
0.2%
N/A
Other
89,891 lines
0.5%
N/A
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I-Shaped Developer
I-shapedSpecialist — deep expertise in Verilog
Verilog
SystemVerilog
C
Makefile
C++
Collaboration Network
Global Impact visualization
Repos
39
PRs
0
Growth
+18%
Top Collaborators
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Coding Streak
Contribution activity over the past year
1 day
118
Contributions
118
Commits
0
Pull Requests
Jun
Jul
Aug
Sep
Oct
Nov
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Jan
Feb
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Apr
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Based on GitHub activity
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Following
51 total
Saute
@Saute0212
Wei Wu
@lazyparser
Inochi Amaoto
@inochisa
denchu314
@denchu314
Masanori Misono
@mmisono
Synced via GitHub
Top Repositories
risc-v
RISC-VのCPU作った
20
0
Verilog
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SPIで制御出来るアクセラレータ
4
0
SystemVerilog
cprv32g
まともなRISC-V CPU
3
1
SystemVerilog
Cra2yPierr0t.github.io
2
2
HTML
cordic
sinを100倍して8bitで即座に計算してくれるやつ
2
0
C++
I_think_it_will_be_Drone
ドローン作るよ
2
0
SystemVerilog
cpu_pipeline
5段パイプラインのRISC-V CPU
2
0
Verilog
caravel_walkthrough_uart
caravel walkthrough for beginners
1
0
Verilog
TOY_TPU
取り敢えず動くTPU
1
0
SystemVerilog
nand2tetris
O'Reilly コンピュータシステムの理論と実装
1
0
C
Open Source Impact
Contributions to external projects
6 merged PRs
VLSI-JP/VLSI-JP.github.io
31
cradsec/cradsec.github.io
0
Commonwealth-of-Processors/.github
0
Commonwealth-of-Processors/CommonGoods
0
Commonwealth-of-Processors/BureCore
0
Contributed to 5 repositories